
import verilog

sf = verilog.SynFlag()

source_f = "source.v"
dest_f = "test.v"

source_f = "/mnt/hgfs/wrok/dev/workspace/cosim_zebu/zebu/xTnC_cpu.v-bak"
dest_f = "/mnt/hgfs/wrok/dev/workspace/cosim_zebu/xTnC_cpu.sv_format"

sf.format(source_f, dest_f)
